In many integrated circuit designs it can be desirable to provide a reference circuit. A reference circuit can provide a current and/or voltage at a generally known value. Reference circuits can have numerous applications, including but not limited to establishing a reference voltage to detect input signal levels, establishing a lower supply voltage to some section of a larger integrated circuit (e.g., memory cell array), establishing a reference voltage/current to determine the logic value stored in a memory cell, establishing a threshold voltage for some other function.
Reference circuits can be non-biased or self-biased. Non-biased reference circuits can rely on discrete voltage drop devices to arrive at a reference level. For example, a non-biased reference circuit can include resistor-diode (or diode connected transistor) arranged in series between a high supply voltage and a low supply voltage. A drawback to such approaches can be that a current drawn can be proportional to supply voltage. Thus, a higher supply voltage can result in a higher device current (ICC). This can be undesirable for low power applications.
Self-biased reference circuits can rely on transistor biasing to provide a reference current that is less variable in response to changes in power supply voltage. Self-biased reference circuits almost always operate in conjunction with a start-up circuit. A start-up circuit can help establish potentials at particular nodes in a power up (or similar operation) in order to ensure that the reference circuit is operating properly. A drawback to conventional self-biased circuits can be that start-up current paths are never shut-off. Thus, such start-up circuits will continue to draw current irrespective of operational mode. This forces the startup current to be relatively low in order to consume low power and hence limits the speed of a start-up operation.
Reference circuits can also be passive or active. A passive reference circuit can remain in the same state regardless of the integrated circuit device mode. Thus, a passive reference circuit can provide a same reference current while power is applied to the corresponding integrated circuit. Such an arrangement can be undesirable in low power devices or require relatively large amounts of device area. For example, while a reference current magnitude can be reduced by employing large resistors, such large resistors can consume a large amount of area and require additional circuitry to generate a larger, more usable current magnitude (i.e., current multipliers).
An active reference circuit can be placed in an enabled mode, in which the reference circuit can provide a reference value at a more practical level (i.e., a reference current that does not require undue multiplication to arrive at a usable level). However, in a disable mode, the reference circuit can be placed into a state that draws essentially no current. Such an arrangement can help reduce current by placing the reference circuit in the disabled mode when not in use.
To better understand various features of the present invention, a conventional reference circuit with corresponding start-up circuitry will now be described. The conventional example represents a “DC” startup circuit that can place a reference circuit in an inactive or active mode based on the logic state of a mode signal (in this case a chip enable signal) and a reference potential.
FIG. 5 shows a conventional reference circuit designated by the general reference character 500. A reference circuit 500 can include an active bias reference stage 502 and a start-up circuit 504. Reference stage 502 can operate in an enabled mode or disabled mode. In an enabled mode, reference stage 502 can draw a current IREF and IMIRR. Such currents can provide a reference value for an integrated circuit either directly or indirectly (e.g., via further current mirroring). In a disabled mode, disable device N53 can be turned on, pulling Node2 to a low supply voltage VGND, turning off n-channel devices (N51 and N52), and thus stopping the generation of currents IREF and IMIRR.
A start-up circuit 504 can include a sensing leg 506, a pull-up leg 508 and a pull-down leg 510. A sensing leg 506 can determine when a reference stage 502 has achieved a start-up state. Once such a determination has been made, a sensing leg 506 can disable the pull-up leg 508 and pull-down leg 510.
In more detail, initially, a chip enable (CE) signal can be at an inactive level (low). In such a condition, signals CEB/CEB2 can be high, while signal CE2 can be low. As noted above, within reference stage 502 disable device N53 can pull Node2 to a ground, disabling current mirror N51/N52, and thus preventing current from being drawn by reference stage 502. Within pull-up stage 508, device P53 can be turned off by signal CEB2, disabling the pull-up path. Similarly, within pull-down stage 510, device N56 can be turned off by signal CE2, disabling the pull-down path. Within sensing leg 506, with Node2 pulled low, device N59 can be turned off, disabling the sensing leg 506.
A device can enter a start-up state by the CE signal transitioning from the inactive level (low) to an active level (high). Signals CEB/CEB2 will transition from high to low, while signal CE2 can transition from low to high. Within reference stage 502, device N53 can be turned off, enabling current mirror N51/N52. Within pull-up stage 508, device P53 can be turned on by signal CEB2, enabling the pull-up path through device N54. Within pull-down stage 510, device N56 can be turned on by signal CE2, enabling the pull-down path through device N57. Thus, Node1 can begin to discharge, while Node2 can begin to charge.
Within sensing leg 506, device N58 can receive a voltage Vlimit at its gate. This can limit the pull-up potential at the source of device N58. Further, device P54 can receive the potential at Node2 at its gate. As a result, an intermediate voltage Vctrl can be generated at Node3.
As the start-up operation proceeds, the potential at Node2 can continue to rise eventually turning on N59 and turning off P54. Thus Vctrl will be switched to VGND eventually, due to the potential Vctrl applied to the gate of device N54, pull-up leg 508 can be disabled, and the pull-up operation at Node2 can cease. Similarly, as the start-up operation proceeds, the potential at Node1 can continue to fall. Eventually, due to the potential Vctrl applied to the gate of device N57 and Vlimit applied to the gate of NV55, the pull-down operation at Node1 can cease. Ideally, the reference stage 502 is operating in a nominal fashion, having switched from a disabled mode to an enabled mode.
While a conventional arrangement like that of FIG. 5 can provide a start-up circuit that can be disabled, such a circuit can have some drawbacks. First, the operation of the circuit can depend on the control bias voltages Vlimit to work properly. Second, such a circuit may have a minimum CE signal disable time. More particularly, when the CE (and CEB) signal goes to a disabled level, it may take some time for Vctrl to reach the Vlimit level. This time period can be considered a “minimum disable time”. If the CE (and CEB) signal goes to an enabled level before such a “minimum disable time”, the circuit may fail to properly initialize Node1 and Node2, and the reference stage 502 will fail to operate properly.